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Freescale Semiconductor Data Sheet: Product Preview
Document Number: K51P81M100SF2 Rev. 4, 3/2011
K51 Sub-Family Data Sheet
Features * Operating Characteristics - Voltage range: 1.71 to 3.6 V - Flash write voltage range: 1.71 to 3.6 V - Temperature range (ambient): -40 to 85C * Performance - Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz * Memories and memory interfaces - Up to 512 KB program flash memory on nonFlexMemory devices - Up to 256 KB program flash memory on FlexMemory devices - Up to 256 KB FlexNVM on FlexMemory devices - 4 KB FlexRAM on FlexMemory devices - Up to 128 KB RAM - Serial programming interface (EzPort) * Clocks - 3 to 32 MHz crystal oscillator - 32 kHz crystal oscillator - Multi-purpose clock generator * System peripherals - 10 low-power modes to provide power optimization based on application requirements - Memory protection unit with multi-master protection - 16-channel DMA controller, supporting up to 64 request sources - External watchdog monitor - Software watchdog - Low-leakage wakeup unit * Security and integrity modules - Hardware CRC module to support fast cyclic redundancy checks - 128-bit unique identification (ID) number per chip
K51P81M100SF2
Supports the following: MK51X256CLK100, MK51X256CMB100
* Human-machine interface - Segment LCD controller supporting up to 40 frontplanes and 8 backplanes, or 44 frontplanes and 4 backplanes - Low-power hardware touch sensor interface (TSI) - General-purpose input/output * Analog modules - Two 16-bit SAR ADCs - Programmable gain amplifier (up to x64) integrated into each ADC - Two 12-bit DACs - Two operational amplifiers - Two transimpedance amplifiers - Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input - Voltage reference * Timers - Programmable delay block - Eight-channel motor control/general purpose/PWM timer - Two 2-channel quadrature decoder/general purpose timers - Periodic interrupt timers - 16-bit low-power timer - Carrier modulator transmitter - Real-time clock * Communication interfaces - USB full-/low-speed On-the-Go controller with onchip transceiver - Two SPI modules - Two I2C modules - Four UART modules - I2S module
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) 2010-2011 Freescale Semiconductor, Inc. Preliminary
Table of Contents
1 Ordering parts...........................................................................4 1.1 Determining valid orderable parts......................................4 2 Part identification......................................................................4 2.1 Description.........................................................................4 2.2 Format...............................................................................4 2.3 Fields.................................................................................4 2.4 Example............................................................................5 3 Terminology and guidelines......................................................5 3.1 Definition: Operating requirement......................................5 3.2 Definition: Operating behavior...........................................6 3.3 Definition: Attribute............................................................6 3.4 Definition: Rating...............................................................7 3.5 Result of exceeding a rating..............................................7 3.6 Relationship between ratings and operating requirements......................................................................7 3.7 Guidelines for ratings and operating requirements............8 3.8 Definition: Typical value.....................................................8 3.9 Typical value conditions....................................................9 4 Ratings......................................................................................9 4.1 Thermal handling ratings...................................................10 4.2 Moisture handling ratings..................................................10 4.3 ESD handling ratings.........................................................10 4.4 Voltage and current operating ratings...............................10 5 General.....................................................................................11 5.1 Nonswitching electrical specifications...............................11 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 Voltage and current operating requirements.........11 LVD and POR operating requirements.................12 Voltage and current operating behaviors..............13 Power mode transition operating behaviors..........13 Power consumption operating behaviors..............14 EMC radiated emissions operating behaviors.......17 Designing with radiated emissions in mind...........18 Capacitance attributes..........................................18 6.6.7 6.6.6 6.1 Core modules....................................................................21 6.1.1 6.1.2 Debug trace timing specifications.........................21 JTAG electricals....................................................21 6.2 System modules................................................................25 6.3 Clock modules...................................................................25 6.3.1 6.3.2 6.3.3 MCG specifications...............................................25 Oscillator electrical specifications.........................27 32kHz Oscillator Electrical Characteristics............29
6.4 Memories and memory interfaces.....................................30 6.4.1 6.4.2 Flash (FTFL) electrical specifications....................30 EzPort Switching Specifications............................34
6.5 Security and integrity modules..........................................35 6.6 Analog...............................................................................35 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 ADC electrical specifications.................................36 CMP and 6-bit DAC electrical specifications.........43 12-bit DAC electrical characteristics.....................46 Op-amp electrical specifications...........................49 Transimpedance amplifier electrical specifications -- full range....................................50 Transimpedance amplifier electrical specifications -- limited range..............................51 Voltage reference electrical specifications............52
6.7 Timers................................................................................53 6.8 Communication interfaces.................................................54 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.8.7 6.8.8 USB electrical specifications.................................54 USB DCD electrical specifications........................54 USB VREG electrical specifications......................54 DSPI switching specifications (low-speed mode)..55 DSPI switching specifications (high-speed mode) 56 I2C switching specifications..................................58 UART switching specifications..............................58 I2S switching specifications..................................58
6.9 Human-machine interfaces (HMI)......................................60 6.9.1 6.9.2 TSI electrical specifications...................................60 LCD electrical characteristics................................61
5.2 Switching specifications.....................................................18 5.2.1 5.2.2 Device clock specifications...................................18 General switching specifications...........................19
7 Dimensions...............................................................................62 7.1 Obtaining package dimensions.........................................62 8 Pinout........................................................................................63 8.1 K51 Signal Multiplexing and Pin Assignments..................63 8.2 K51 Pinouts.......................................................................67
5.3 Thermal specifications.......................................................20 5.3.1 5.3.2 Thermal operating requirements...........................20 Thermal attributes.................................................20
6 Peripheral operating requirements and behaviors....................20
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9 Revision History........................................................................68
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
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Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK51 and MK51.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q K## M Qualification status Kinetis family Flash memory type Description Values * M = Fully qualified, general market flow * P = Prequalification * K51 * N = Program flash only * X = Program flash and FlexMemory Table continues on the next page...
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Terminology and guidelines Field FFF Description Program flash memory size * * * * * * 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB Values
T PP
Temperature range (C) Package identifier
* V = -40 to 105 * C = -40 to 85 * * * * * * * * * * * * * * * * * * FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) EX = 64 QFN (9 mm x 9 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm) MB = 81 MAPBGA (8 mm x 8 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MF = 196 MAPBGA (15 mm x 15 mm) MJ = 256 MAPBGA (17 mm x 17 mm) 50 = 50 MHz 72 = 72 MHz 100 = 100 MHz 120 = 120 MHz 150 = 150 MHz
CCC
Maximum CPU frequency (MHz)
N
Packaging type
* R = Tape and reel * (Blank) = Trays
2.4 Example
This is an example part number: MK51N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
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Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed:
Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements:
Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. A Unit
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digital pins -- Min. 7 Max. pF Unit
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Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol VDD Description 1.0 V core supply voltage -0.3 Min. 1.2 Max. V Unit
3.5 Result of exceeding a rating
40 Failures in time (ppm) 30
20
The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
10
0 Operating rating Measured characteristic
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Terminology and guidelines
3.6 Relationship between ratings and operating requirements
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Fatal range
- Probable permanent failure
Limited operating range
- No permanent failure - Possible decreased life - Possible incorrect operation
Normal operating range
- No permanent failure - Correct operation
Limited operating range
- No permanent failure - Possible decreased life - Possible incorrect operation
Fatal range
- Probable permanent failure
Handling range
- No permanent failure -
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
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Ratings Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. A Unit
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions:
5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 C 105 C 25 C -40 C
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified):
Symbol TA VDD Description Ambient temperature 3.3 V supply voltage 25 3.3 Value C V Unit
4 Ratings
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Ratings
4.1 Thermal handling ratings
Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. -55 -- -- Max. 150 260 245 Unit C C Notes 1 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol MSL Description Moisture sensitivity level Min. -- Max. 3 Unit -- Notes 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 85C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol VDD IDD VDIO Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Table continues on the next page... Min. -0.3 -- -0.3 Max. 3.8 185 5.5 Unit V mA V
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General Symbol VAIO ID VDDA VUSB_DP VUSB_DM VREGIN VBAT Description Analog, RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage USB_DP input voltage USB_DM input voltage USB regulator input RTC battery supply voltage Min. -0.3 -25 VDD - 0.3 -0.3 -0.3 -0.3 -0.3 Max. VDD + 0.3 25 VDD + 0.3 3.63 3.63 6.0 3.8 Unit V mA V V V V V
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 -0.1 -0.1 1.71 Max. 3.6 3.6 0.1 0.1 3.6 Unit V V V V V Notes
VDD - VDDA VDD-to-VDDA differential voltage VSS - VSSA VSS-to-VSSA differential voltage VBAT VIH RTC battery supply voltage Input high voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VIL Input low voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VHYS Input hysteresis
0.7 x VDD 0.75 x VDD
-- --
V V
-- -- 0.06 x VDD Table continues on the next page...
0.35 x VDD 0.3 x VDD --
V V V
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General
Table 1. Voltage and current operating requirements (continued)
Symbol IIC Description DC injection current -- single pin * VIN < VSS DC injection current -- total MCU limit, includes sum of all stressed pins * VIN < VSS VRAM VRFVBAT VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file 0 -0.2 mA 1 0 1.2 TBD -5 -- -- mA V V Min. Max. Unit Notes 1
1. All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The IIC maximum operating requirement should not be exceeded. If this requirement cannot be met, the input must be current limited to the value specified.
5.1.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold -- high range (LVDV=01) Low-voltage warning thresholds -- high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL * Level 1 falling (LVWV=00) * Level 2 falling (LVWV=01) * Level 3 falling (LVWV=10) * Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis -- high range Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO * Level 1 falling (LVWV=00) * Level 2 falling (LVWV=01) * Level 3 falling (LVWV=10) * Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis -- low range Bandgap voltage reference Internal low power oscillator period factory trimmed TBD TBD TBD TBD TBD TBD 1.80 1.90 2.00 2.10 40 1.00 1000 TBD TBD TBD TBD TBD TBD V V V V mV V s TBD TBD TBD TBD TBD 2.70 2.80 2.90 3.00 60 1.60 TBD TBD TBD TBD TBD V V V V mV V 1 Min. TBD TBD Typ. 1.1 2.56 Max. TBD TBD Unit V V 1 Notes
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General 1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. TBD Typ. 1.1 Max. TBD Unit V Notes VPOR_VBAT Falling VBAT supply POR detect voltage
5.1.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol VOH Description Output high voltage -- high drive strength * 2.7 V VDD 3.6 V, IOH = -10mA * 1.71 V VDD 2.7 V, IOH = -3mA Output high voltage -- low drive strength * 2.7 V VDD 3.6 V, IOH = -2mA * 1.71 V VDD 2.7 V, IOH = -0.6mA IOHT VOL Output high current total for all ports Output low voltage -- high drive strength * 2.7 V VDD 3.6 V, IOL = 10mA * 1.71 V VDD 2.7 V, IOL = 3mA Output low voltage -- low drive strength * 2.7 V VDD 3.6 V, IOL = 2mA * 1.71 V VDD 2.7 V, IOL = 0.6mA IOLT IIN IILKG_A IOZ RPU RPD Output low current total for all ports Input leakage current (per pin) except TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP Input leakage current (per pin) for TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP Hi-Z (off-state) leakage current (per pin) Internal pullup resistors Internal pulldown resistors -- -- -- -- -- -- 30 30 0.5 0.5 100 1 1 1 50 50 V V mA A nA A k k 2 3 1 1 -- -- 0.5 0.5 V V VDD - 0.5 VDD - 0.5 -- -- -- 100 V V mA VDD - 0.5 VDD - 0.5 -- -- V V Min. Max. Unit Notes
1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD
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General
5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 100 MHz * Bus clock = 50 MHz * Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8V to execution of the first instruction across the operating temperature range of the chip. RUN VLLS1 RUN * RUN VLLS1 * VLLS1 RUN RUN VLLS2 RUN * RUN VLLS2 * VLLS2 RUN RUN VLLS3 RUN * RUN VLLS3 * VLLS3 RUN RUN LLS RUN * RUN LLS * LLS RUN RUN STOP RUN * RUN STOP * STOP RUN RUN VLPS RUN * RUN VLPS * VLPS RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) -- -- 4.1 5.8 s s -- -- 4.1 4.2 s s -- -- 4.1 5.9 s s -- -- 4.1 49.2 s s -- -- 4.1 49.3 s s -- -- 4.1 123.8 s s Min. -- Max. 300 Unit s Notes 1
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General
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol IDDA IDD_RUN Description Analog supply current Run mode current -- all peripheral clocks disabled, code executing from flash * @ 1.8V * @ 3.0V IDD_RUN Run mode current -- all peripheral clocks enabled, code executing from flash * @ 1.8V * @ 3.0V IDD_RUN_M Run mode current -- all peripheral clocks enabled and peripherals active, code executing AX from flash * @ 1.8V * @ 3.0V IDD_WAIT IDD_WAIT IDD_STOP IDD_VLPR IDD_VLPR IDD_VLPW IDD_VLPS IDD_LLS IDD_VLLS3 Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled Stop mode current at 3.0 V Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled Very-low-power wait mode current at 3.0 V Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V * 64KB RAM devices IDD_VLLS2 IDD_VLLS1 IDD_VBAT Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V -- -- -- -- 6 4 2 550 TBD TBD TBD TBD A A A nA 9 -- -- 55 56 TBD TBD mA mA 4 -- -- -- -- -- -- -- -- -- -- 85 85 35 15 0.4 1.25 TBD 1.05 50 12 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA A A 6 7 8 2 5 -- -- 40 42 TBD TBD mA mA 3 Min. -- Typ. -- Max. TBD Unit mA Notes 1 2
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation.
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General 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation.
5.1.5.1 * * * * *
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks disabled except FTFL LVD disabled, USB regulator disabled No GPIOs toggled Code execution from flash
Figure 1. Run mode supply current vs. core frequency -- all peripheral clocks disabled
The following data was measured under these conditions:
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* * * * *
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks enabled but peripherals are not in active operation LVD disabled, USB regulator disabled No GPIOs toggled Code execution from flash
Figure 2. Run mode supply current vs. core frequency -- all peripheral clocks enabled
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General
5.1.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol VRE1 VRE2 VRE3 VRE4 Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 Frequency band (MHz) 0.15-50 50-150 150-500 500-1000 0.15-1000 Typ. TBD TBD TBD TBD TBD -- 2, 3 Unit dBV Notes 1, 2
VRE_IEC_SAE IEC and SAE level
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/ Wideband TEM (GTEM) Cell Method. 2. VDD = 3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = 96 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for "EMC design."
5.1.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. -- -- Max. 7 7 Unit pF pF
5.2 Switching specifications
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General
5.2.1 Device clock specifications
Symbol Description Normal run mode fSYS fSYS_USB fBUS fFLASH System and core clock System and core clock when USB in operation Bus clock Flash clock VLPR mode fSYS fBUS fFLASH System and core clock Bus clock Flash clock -- -- -- 2 2 1 MHz MHz MHz -- 20 -- -- 100 -- 50 25 MHz MHz MHz MHz Min. Max. Unit Notes
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART, CMT, and I2C signals.
Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) -- Asynchronous path GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) -- Asynchronous path External reset pulse width (digital glitch filter disabled) Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) * Slew disabled * Slew enabled Port rise and fall time (low drive strength) * Slew disabled * Slew enabled 1. 2. 3. 4. The greater synchronous and asynchronous timing must be met. This is the shortest pulse that is guaranteed to be recognized. 75pF load 15pF load -- -- 32 36 ns ns -- -- 12 36 ns ns 4 Min. 1.5 100 16 TBD 2 Max. -- -- -- -- -- Bus clock cycles 3 Unit Bus clock cycles ns ns Notes 1 2
2
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Peripheral operating requirements and behaviors
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol TJ TA Description Die junction temperature Ambient temperature Min. -40 -40 Max. 125 85 Unit C C
5.3.2 Thermal attributes
Board type
Singlelayer (1s) Four-layer (2s2p) Singlelayer (1s) Four-layer (2s2p) -- -- -- 1.
Symbol
RJA RJA RJMA RJMA RJB RJC JT
Description
Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./ min. air speed) Thermal resistance, junction to ambient (200 ft./ min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection)
81 80 LQFP Unit MAPBGA
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD C/W C/W C/W C/W C/W C/W C/W
Notes
1 1 1 1 2 3 4
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume: 1. output pins * have CL=30pF loads, * are configured for fast slew rate (PORTx_PCRn[SRE]=0), and * are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
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Peripheral operating requirements and behaviors
* have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol Tcyc Twl Twh Tr Tf Ts Th Description Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold Min. Max. Unit MHz ns ns ns ns ns ns Frequency dependent 2 2 -- -- 3 2 -- -- 3 3 -- --
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts Th Ts Th
TRACE_D[3:0]
Figure 4. Trace data specifications
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
21
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
Symbol Description Operating voltage J1 TCLK frequency of operation * Boundary Scan * JTAG and CJTAG * Serial Wire Debug J2 J3 TCLK cycle period TCLK clock pulse width * Boundary Scan * JTAG and CJTAG * Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high 50 20 10 -- 20 0 -- -- 8 1 -- -- 100 8 3 -- -- 25 25 -- -- 17 17 -- -- ns ns ns ns ns ns ns ns ns ns ns -- -- 0 0 0 1/J1 10 25 50 -- ns ns Min. 2.7 Max. 3.6 Unit V MHz
Table 12. JTAG full voltage range electricals
Symbol Description Operating voltage J1 TCLK frequency of operation * Boundary Scan * JTAG and CJTAG * Serial Wire Debug J2 TCLK cycle period Table continues on the next page... 0 0 0 1/J1 10 20 40 -- ns Min. 1.71 Max. 3.6 Unit V MHz
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Peripheral operating requirements and behaviors
Table 12. JTAG full voltage range electricals (continued)
Symbol J3 Description TCLK clock pulse width * Boundary Scan * JTAG and CJTAG * Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high 50 25 12.5 -- 20 0 -- -- 8 1.4 -- -- 100 8 3 -- -- 25 25 -- -- 22.1 22.1 -- -- ns ns ns ns ns ns ns ns ns ns ns -- -- Min. Max. Unit ns
J2 J3 J3
TCLK (input)
J4
J4
Figure 5. Test clock input timing
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
23
Peripheral operating requirements and behaviors
TCLK
J5 J6
Data inputs
J7
Input data valid
Data outputs
J8
Output data valid
Data outputs
J7
Data outputs
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
J9 J10
TDI/TMS
J11
Input data valid
TDO
J12
Output data valid
TDO
J11
TDO
Output data valid
Figure 7. Test Access Port timing
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14 J13
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol fints_ft fints_t Iints tirefsts fdco_res_t Description Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25C Internal reference frequency (slow clock) -- user trimmed Internal reference (slow clock) current Internal reference (slow clock) startup time Resolution of trimmed DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM Resolution of trimmed DCO output frequency at fixed voltage and temperature -- using SCTRIM only Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C Internal reference frequency (fast clock) -- user trimmed Min. -- 31.25 -- -- -- Typ. 32.768 -- TBD TBD 0.1 Max. -- 39.0625 -- 4 0.3 Unit kHz kHz A s %fdco 1 Notes
fdco_res_t
--
0.2
0.5
%fdco
1
fdco_t fdco_t
--
+ 0.5 - 1.0
3.5
%fdco %fdco
1
--
0.5
TBD
1
fintf_ft fintf_t
3.4 3
-- --
4 5
MHz MHz
Table continues on the next page...
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Preliminary
25
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Iintf tirefstf floc_low floc_high Description Internal reference (fast clock) current Internal reference startup time (fast clock) Loss of external clock minimum frequency -- RANGE = 00 Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll Jacc_fll tfll_acquire FLL period jitter FLL accumulated jitter of DCO output over a 1s time window FLL target frequency acquisition time PLL fvco Ipll VCO operating frequency PLL operating current * PLL @ 96 MHz (fosc_hi_1=8MHz, fpll_ref=2MHz, VDIV multiplier=48) PLL reference frequency range PLL period jitter PLL accumulated jitter over 1s window 48.0 -- -- 950 100 -- MHz A 8 -- -- -- TBD TBD -- TBD TBD 1 ps ps ms 6 6 7 -- 95.98 -- MHz -- 71.99 -- MHz -- 47.97 -- MHz -- 23.99 -- MHz 4, 5 80 83.89 100 MHz 60 62.91 75 MHz 40 41.94 50 MHz 31.25 20 -- 20.97 39.0625 25 kHz MHz 2, 3 Min. -- -- (3/5) x fints_t (16/5) x fints_t Typ. TBD TBD -- -- Max. -- TBD -- -- Unit A s kHz kHz Notes
fpll_ref Jcyc_pll Jacc_pll
2.0 -- --
-- 400 TBD
4.0 -- --
MHz ps ps 9, 10 9, 10
Table continues on the next page...
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Dlock Dunl tpll_lock Description Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time Min. 1.49 4.47 -- Typ. -- -- -- Max. 2.98 5.97 0.15 + 1075(1/ fpll_ref) Unit % % ms 11 Notes
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification was obtained at internal frequency of TBD. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module. 6.3.2.1
Symbol VDD IDDOSC
Oscillator DC electrical specifications
Description Supply voltage Supply current -- low-power mode (HGO=0) * 32 kHz * 4 MHz * 8 MHz * 16 MHz * 24 MHz * 32 MHz -- -- -- -- -- -- Min. 1.71
Table 14. Oscillator DC electrical specifications
Typ. -- Max. 3.6 Unit V 1 500 200 300 700 1.2 1.5 -- -- -- -- -- -- nA A A A mA mA Notes
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Preliminary
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Peripheral operating requirements and behaviors
Table 14. Oscillator DC electrical specifications (continued)
Symbol IDDOSC Description Supply current -- high gain mode (HGO=1) * 32 kHz * 4 MHz * 8 MHz * 16 MHz * 24 MHz * 32 MHz Cx Cy RF EXTAL load capacitance XTAL load capacitance Feedback resistor -- low-frequency, low-power mode (HGO=0) Feedback resistor -- low-frequency, high-gain mode (HGO=1) Feedback resistor -- high-frequency, low-power mode (HGO=0) Feedback resistor -- high-frequency, high-gain mode (HGO=1) RS Series resistor -- low-frequency, low-power mode (HGO=0) Series resistor -- low-frequency, high-gain mode (HGO=1) Series resistor -- high-frequency, low-power mode (HGO=0) Series resistor -- high-frequency, high-gain mode (HGO=1) -- Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) 1. 2. 3. 4. -- 0 0.6 -- -- k V -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 400 800 1.5 3 4 -- -- -- 10 -- 1 -- 200 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M M M M k k k A A A mA mA mA 2, 3 2, 3 2, 4 Min. Typ. Max. Unit Notes 1
--
VDD
--
V
--
0.6
--
V
--
VDD
--
V
VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.
6.3.2.2
Symbol fosc_lo fosc_hi_1
Oscillator frequency specifications
Description Oscillator crystal or resonator frequency -- low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency -- high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 3
Table 15. Oscillator frequency specifications
Typ. -- -- Max. 40 8 Unit kHz MHz Notes
fosc_hi_2
8
--
32
MHz
fec_extal tdc_extal tcst
-- 40 -- -- --
-- 50 TBD 800 4
50 60 -- -- --
MHz % ms ms ms
1
2, 3
--
3
--
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics. 6.3.3.1
Symbol VBAT RF Cpara
32kHz oscillator DC electrical specifications
Description Supply voltage Internal feedback resistor Parasitical capacitance of EXTAL32 and XTAL32 Min. 1.71 -- --
Table 16. 32kHz oscillator DC electrical specifications
Typ. -- 100 2.5 Max. 3.6 -- -- Unit V M pF
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Preliminary
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Peripheral operating requirements and behaviors
Table 16. 32kHz oscillator DC electrical specifications (continued)
Symbol Cload Vpp Description Internal load capacitance (programmable) Peak-to-peak amplitude of oscillation Min. -- -- Typ. 15 0.6 Max. -- -- Unit pF V
6.3.3.2
Symbol fosc_lo tstart
32kHz oscillator frequency specifications
Description Oscillator crystal Crystal start-up time Min. -- --
Table 17. 32kHz oscillator frequency specifications
Typ. 32 1000 Max. -- -- Unit kHz ms 1 Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash timing specifications -- program and erase
The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.
Table 18. NVM program/erase timing specifications
Symbol thvpgm4 thversscr Description Longword Program high-voltage time Sector Erase high-voltage time Min. -- -- -- Typ. 20 20 160 Max. TBD 100 800 Unit s ms ms 1 1 Notes
thversblk256k Erase Block high-voltage time for 256 KB 1. Maximum time based on expectations at cycling end-of-life.
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Peripheral operating requirements and behaviors
6.4.1.2
Symbol
Flash timing specifications -- commands
Description Read 1s Block execution time Min.
Table 19. Flash command timing specifications
Typ. Max. Unit Notes
trd1blk256k trd1sec2k tpgmchk trdrsrc tpgm4
* 256 KB data flash Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Block execution time
-- -- -- -- --
-- -- -- -- 50
1.4 40 35 35 TBD
ms s s s s 2 1 1 1
tersblk256k tersscr
* 256 KB data flash Erase Flash Sector execution time Program Section execution time
-- --
160 20
800 100
ms ms 2
tpgmsec512 tpgmsec1k tpgmsec2k trd1all trdonce tpgmonce tersall tvfykey
* 512 B flash * 1 KB flash * 2 KB flash Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Program Partition for EEPROM execution time
-- -- -- -- -- -- -- --
TBD TBD TBD -- -- 50 320 --
TBD TBD TBD 2.8 35 TBD 1600 35
ms ms ms ms s s ms s 2 1 1
tpgmpart256k
* 256 KB FlexNVM Set FlexRAM Function execution time:
--
175
TBD
ms
tsetram32k tsetram256k
* 32 KB EEPROM backup * 256 KB EEPROM backup
-- --
TBD TBD
TBD TBD
ms ms
Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time Byte-write to FlexRAM execution time: teewr8b32k teewr8b64k teewr8b128k teewr8b256k * 32 KB EEPROM backup * 64 KB EEPROM backup * 128 KB EEPROM backup * 256 KB EEPROM backup -- -- -- -- TBD TBD TBD TBD TBD 1.5 TBD 2.5 ms ms ms ms -- 100 TBD s 3
Word-write to FlexRAM for EEPROM operation Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 19. Flash command timing specifications (continued)
Symbol teewr16bers Description Word-write to erased FlexRAM location execution time Word-write to FlexRAM execution time: teewr16b32k teewr16b64k teewr16b128k teewr16b256k * 32 KB EEPROM backup * 64 KB EEPROM backup * 128 KB EEPROM backup * 256 KB EEPROM backup -- -- -- -- TBD TBD TBD TBD TBD 1.5 TBD 2.5 ms ms ms ms Min. -- Typ. 100 Max. TBD Unit s Notes
Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time Longword-write to FlexRAM execution time: teewr32b32k teewr32b64k teewr32b128k teewr32b256k * 32 KB EEPROM backup * 64 KB EEPROM backup * 128 KB EEPROM backup * 256 KB EEPROM backup -- -- -- -- TBD TBD TBD TBD TBD 2.7 TBD 3.7 ms ms ms ms -- 200 TBD s
1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash (FTFL) current and power specfications
Description Worst case programming current in program flash
Table 20. Flash (FTFL) current and power specfications
Typ. 10 Unit mA
Symbol IDD_PGM
6.4.1.4
Symbol
Reliability specifications
Description
Table 21. NVM reliability specifications
Min. Program Flash Typ.1 Max. Unit Notes
tnvmretp10k tnvmretp1k tnvmretp100 nnvmcycp
Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance
5 10 15 10 K Data Flash
TBD TBD TBD TBD
-- -- -- --
years years years cycles
2 2 2 3
tnvmretd10k
Data retention after up to 10 K cycles
5
TBD
--
years
2
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 21. NVM reliability specifications (continued)
Symbol tnvmretd1k tnvmretd100 nnvmcycd Description Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance Min. 10 15 10 K FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance tnvmretee10 tnvmretee1 Data retention up to 10% of write endurance Data retention up to 1% of write endurance Write endurance nnvmwree16 nnvmwree128 nnvmwree512 nnvmwree4k nnvmwree32k * EEPROM backup to FlexRAM ratio = 16 * EEPROM backup to FlexRAM ratio = 128 * EEPROM backup to FlexRAM ratio = 512 * EEPROM backup to FlexRAM ratio = 4096 * EEPROM backup to FlexRAM ratio = 32,768 35 K 315 K 1.27 M 10 M 80 M TBD TBD TBD TBD TBD -- -- -- -- -- writes writes writes writes writes 5 10 15 TBD TBD TBD -- -- -- years years years 2 2 2 4 Typ.1 TBD TBD TBD Max. -- -- -- Unit years years cycles Notes 2 2 3
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 4. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum value assumes all byte-writes to FlexRAM.
6.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used.
Writes_subsystem = EEPROM - 2 x EEESPLIT x EEESIZE EEESPLIT x EEESIZE x Write_efficiency x nnvmcycd
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Peripheral operating requirements and behaviors
where * Writes_subsystem -- minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) * EEPROM -- allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command * EEESPLIT -- FlexRAM split factor for subsystem; entered with the Program Partition command * EEESIZE -- allocated FlexRAM based on DEPART; entered with Program Partition command * Write_efficiency -- * 0.25 for 8-bit writes to FlexRAM * 0.50 for 16-bit or 32-bit writes to FlexRAM * nnvmcycd -- data flash cycling endurance
Figure 9. EEPROM backup writes to FlexRAM
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Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num Description Operating voltage EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid (setup) EZP_CK low to EZP_Q output invalid (hold) EZP_CS negation to EZP_Q tri-state Min. 2.7 -- -- 2 x tEZP_CK 5 5 2 5 -- 0 -- Max. 3.6 fSYS/2 fSYS/8 -- -- -- -- -- 12 -- 12 Unit V MHz MHz ns ns ns ns ns ns ns ns
EZP_CK
EP3 EP4 EP2
EZP_CS
EP7 EP8
EP9
EZP_Q (output)
EP5 EP6
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
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Preliminary
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Peripheral operating requirements and behaviors
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DP3. The ADCx_DP2 and ADCx_DM2 ADC inputs are used as the PGA inputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 25 and Table 26. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1
Symbol VDDA VDDA VSSA VREFH VREFL VADIN CADIN
16-bit ADC operating conditions
Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Reference voltage low Input voltage Input capacitance * 16 bit modes * 8/10/12 bit modes Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 VSSA VREFL -- --
Table 23. 16-bit ADC operating conditions
Typ.1 -- 0 0 VDDA VSSA -- 8 4 Max. 3.6 +100 +100 VDDA VSSA VREFH 10 5 Unit V mV mV V V V pF 2 2 Notes
RADIN RAS
Input resistance Analog source resistance 13/12 bit modes fADCK < 4MHz 13 bit modes
--
2
5
k 3
--
--
5
k
fADCK fADCK
ADC conversion clock frequency ADC conversion clock frequency
4 1.0 -- 18.0 MHz 5 2.0 -- 12.0 MHz
16 bit modes
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Symbol Crate Description ADC conversion rate Conditions 13 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50MHz Crate ADC conversion rate 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50MHz 1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has <8 analog source resistance. The RAS/ CAS time constant should be kept to <1ns. 4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear. 5. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear. 6. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 37.037 -- 361.402 Ksps 7 18.484 -- 818.330 Ksps Min. Typ.1 Max. Unit Notes 6
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
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Peripheral operating requirements and behaviors
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT
Z ADIN
SIMPLIFIED CHANNEL SELECT CIRCUIT
Z AS R AS V ADIN V AS C AS
Pad leakage due to input protection
R ADIN
ADC SAR ENGINE
R ADIN INPUT PIN
R ADIN
INPUT PIN
R ADIN C ADIN
INPUT PIN
Figure 11. ADC input impedance equivalency diagram
6.6.1.2
Symbol IDDA
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Description Supply current ADC asynchronous clock source * ADLPC=1, ADHSC=0 * ADLPC=1, ADHSC=1 * ADLPC=0, ADHSC=0 * ADLPC=0, ADHSC=1 Sample Time Conditions1 Min. 0.215 -- -- -- -- Typ.2 -- 2.4 4.0 5.2 6.2 Max. 1.7 -- -- -- -- Unit mA MHz MHz MHz MHz Notes 3 tADACK = 1/ fADACK
16-bit ADC electrical characteristics
fADACK
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/ converters/ADC_CALCULATOR_CNV.zip?fpsp=1 TUE Total unadjusted error * 13 bit modes * <12 bit modes 0.8 0.5 TBD 1 LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
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Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol DNL Description Differential nonlinearity Conditions1 * 13 bit modes * <12 bit modes Min. Typ.2 0.7 0.2 Max. TBD 0.5 Unit LSB4 Notes ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Max averaging VADIN = VDDA
INL
Integral nonlinearity Full-scale error
* 13 bit modes * <12 bit modes * 13 bit modes * <12 bit modes
-- -- -- -- -- --
1.0 0.5 0.4 1.0 -1 to 0 --
TBD TBD TBD TBD -- 0.5
LSB4
EFS EQ
LSB4
Quantization error
* 16 bit modes * 13 bit modes
LSB4
ENOB
Effective number 16 bit differential mode of bits * Avg=32 * Avg=1 16 bit single-ended mode * Avg=32 * Avg=1
5 TBD TBD 13.6 13.2 TBD TBD bits bits
TBD TBD
TBD TBD 6.02 x ENOB + 1.76
TBD TBD
bits bits dB 5
SINAD THD
Signal-to-noise plus distortion Total harmonic distortion
See ENOB 16 bit differential mode * Avg=32 16 bit single-ended mode * Avg=32 -- --
-94 TBD
TBD TBD
dB dB 5
SFDR
Spurious free dynamic range
16 bit differential mode * Avg=32 16 bit single-ended mode * Avg=32 TBD TBD -- dB TBD 95 -- dB
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Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol EIL Description Input leakage error Conditions1 Min. Typ.2 IIn x RAS Max. Unit mV Notes IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage * -40C to 25C * 25C to 105C 25C -- -- -- TBD TBD TBD -- -- -- mV/C mV/C mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. Input data is 1 kHz sine wave.
FIGURE TBD
Figure 12. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
FIGURE TBD
Figure 13. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended modes
6.6.1.3
Symbol VDDA VREFPGA VADIN VCM
16-bit ADC with PGA operating conditions
Description Supply voltage PGA ref voltage Input voltage Input Common Mode range Conditions Absolute Min. 1.71 Typ.1 --
Table 25. 16-bit ADC with PGA operating conditions
Max. 3.6 Unit V V V V 2, 3 Notes
VREFOUT VREFOUT VREFOUT VSSA VSSA -- -- VDDA VDDA
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Table 25. 16-bit ADC with PGA operating conditions (continued)
Symbol RPGAD Description Differntial input impedance Conditions Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64 RAS TS Analog source resistance ADC sampling time Min. -- -- -- -- 1.25 Typ.1 128 64 32 100 -- Max. -- -- -- -- -- s 5 6 Unit k Notes IN+ to IN-4
1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREFOUT) 3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedence of the driven input is 1/2. 5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock.
6.6.1.4
Symbol IDDA_PGA IDC_PGA IILKG G
16-bit ADC with PGA characteristics
Description Supply current Input DC current Input Leakage current Gain4 PGA disabled * PGAG=0 * PGAG=1 * PGAG=2 * PGAG=3 * PGAG=4 * PGAG=5 * PGAG=6 -- TBD TBD TBD TBD TBD TBD TBD -- -- TBD Conditions Min. --
Table 26. 16-bit ADC with PGA characteristics
Typ.1 590 Max. TBD Unit A A TBD 0.98 1.99 3.97 7.95 15.8 31.4 61.2 -- -- TBD TBD TBD TBD TBD TBD TBD TBD TBD 4 40 -- kHz kHz dB VDDA= 3V 100mV, fVDDA= 50Hz, 60Hz A 2 3 RAS < 100 Notes
BW
Input signal bandwidth Power supply rejection ration
* 16-bit modes * < 16-bit modes Gain=1
PSRR
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Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol CMRR Description Common mode rejection ratio Conditions * Gain=1 * Gain=64 Min. TBD TBD Typ.1 TBD TBD Max. -- -- Unit dB dB Notes VCM= 500mVpp, fVCM= 50Hz, 100Hz Gain=1, ADC Averaging=32 5 0 to 50C
VOFS TGSW dG/dT
Input offset voltage Gain switching settling time Gain drift over temperature Offset drift over temperature Gain drift over supply voltage Input leakage error * Gain=1 * Gain=64 Gain=1 * Gain=1 * Gain=64 All modes
-- -- -- -- -- -- --
0.2 -- TBD TBD TBD TBD TBD IIn x RAS
TBD 10 TBD TBD TBD TBD TBD
mV s ppm/C ppm/C ppm/C %/V %/V mV
dVOFS/dT dG/dVDDA EIL
0 to 50C, ADC Averaging=32 VDDA from 1.71 to 3.6V IIn = leakage current (refer to the MCU's voltage and current operating ratings)
VPP,DIFF
Maximum differential input signal swing Signal-to-noise ratio * Gain=1 * Gain=64
V where VX = VREFPGA x 0.583 TBD TBD 83.0 57.5 -- -- dB dB
6
SNR
16-bit differential mode, Average=32 16-bit differential mode, Average=32, fin=500Hz 16-bit differential mode, Average=32, fin=500Hz
THD
Total harmonic distortion
* Gain=1 * Gain=64
TBD TBD
89.4 90.0
-- --
dB dB
SFDR
Spurious free dynamic range
* Gain=1 * Gain=64
TBD TBD
90.9 77.0
-- --
dB dB
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Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol ENOB Description Effective number of bits Conditions * Gain=1, Average=4 * Gain=1, Average=8 * Gain=64, Average=4 * Gain=64, Average=8 * Gain=1, Average=32 * Gain=2, Average=32 * Gain=4, Average=32 * Gain=8, Average=32 * Gain=16, Average=32 * Gain=32, Average=32 * Gain=64, Average=32 SINAD Signal-to-noise plus distortion ratio See ENOB Min. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Typ.1 12.3 12.7 8.4 8.7 13.3 13.1 12.5 11.8 11.1 10.2 9.3 Max. -- -- -- -- -- -- -- -- -- -- -- Unit bits bits bits bits bits bits bits bits bits bits bits dB Notes 16-bit differential mode, fin=500Hz
6.02 x ENOB + 1.76
1. Typical values assume VDDA =3.0V, Temp=25C, fADCK=6MHz unless otherwise stated. 2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function if input common mode voltage (VCM) and the PGA gain. 3. This is the input leakage current of the module in addition to the PAD leakage current. 4. Gain = 2PGAG 5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC sampling rate and time of the switching). 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol VDD IDDHS IDDLS VAIN VAIO Description Supply voltage Supply current, High-speed mode (EN=1, PMODE=1) Supply current, low-speed mode (EN=1, PMODE=0) Analog input voltage Analog input offset voltage Min. 1.71 -- -- VSS - 0.3 -- Table continues on the next page... Typ. -- -- -- -- -- Max. 3.6 200 20 VDD 20 Unit V A A V mV
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Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol VH Description Analog comparator hysteresis1 * CR0[HYSTCTR] = 00 * CR0[HYSTCTR] = 01 * CR0[HYSTCTR] = 10 * CR0[HYSTCTR] = 11 VCMPOh VCMPOl tDHS tDLS Output high Output low Propagation delay, high-speed mode (EN=1, PMODE=1) Propagation delay, low-speed mode (EN=1, PMODE=0) Analog comparator initialization delay2 IDAC6b INL DNL 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity 6-bit DAC differential non-linearity -- -- -- -- VDD - 0.5 -- 20 120 -- -- -0.5 -0.3 5 10 20 30 -- -- 50 250 -- 7 -- -- -- -- -- -- -- 0.5 200 600 TBD -- 0.5 0.3 mV mV mV mV V V ns ns ns A LSB3 LSB Min. Typ. Max. Unit
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64
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0.08 0.07 0.06 0.05
CM P Hystereris (V)
HYSTCTR Setting
00 01
10
0.04 0.03 0.02 0.01 0
11
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Peripheral operating requirements and behaviors
0.18 0.16 0.14 0.12
CMP Hystereris (V) P
HYSTCTR Setting
00 01 10 11
0.1 0 08 0.08 0.06 0.04 0.02 0
0.1
0.4
0.7
1
1.3
Vin level (V)
1.6
1.9
2.2
2.5
2.8
3.1
Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol VDDA VDACR TA CL IL
12-bit DAC operating requirements
Desciption Supply voltage Reference voltage Temperature Output load capacitance Output load current
Table 28. 12-bit DAC operating requirements
Min. 1.71 1.13 -40 -- -- Max. 3.6 3.6 105 100 1 Unit V V C pF mA 2 1 Notes
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
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6.6.3.2
Symbol
12-bit DAC operating behaviors
Description
Table 29. 12-bit DAC operating behaviors
Min. -- -- -- -- -- 1 -- VDACR -100 -- -- -- 0.4 0.1 60 -- -- -- -- TBD TBD -- -- Typ. -- -- 100 15 -- TBD 100 -- -- -- -- -- -- Max. 150 700 200 30 5 -- TBD VDACR 8 1 1 0.8 0.6 90 -- -- TBD 250 Unit A A s s s s mV mV LSB LSB LSB %FSR %FSR dB V/C ppm of FSR/C V/yr V/s 1.2 0.05 -- 1.7 0.12 -- -- -- -80 dB kHz 550 40 -- -- -- -- 2 3 4 5 5 1 1 1 1 Notes
IDDA_DACLP Supply current -- low-power mode IDDA_DACH Supply current -- high-speed mode
P
tDACLP tDACHP tCCDACLP tCCDACHP Vdacoutl Vdacouth INL DNL DNL VOFFSET EG PSRR TCO TGE AC Rop SR
Full-scale settling time (0x080 to 0xF7F) -- lowpower mode Full-scale settling time (0x080 to 0xF7F) -- highpower mode Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode Code-to-code settling time (0xBF8 to 0xC08) -- high-speed mode DAC output voltage range low -- high-speed mode, no load, DAC set to 0x000 DAC output voltage range high -- high-speed mode, no load, DAC set to 0xFFF Integral non-linearity error -- high speed mode Differential non-linearity error -- VDACR > 2 V Differential non-linearity error -- VDACR = VREFO (1.15 V) Offset error Gain error Power supply rejection ratio, VDDA > = 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Offset aging coefficient Output resistance load = 3 k Slew rate -80h F7Fh 80h * High power (SPHP) * Low power (SPLP)
CT BW
Channel to channel cross talk 3dB bandwidth * High power (SPHP) * Low power (SPLP)
1. 2. 3. 4.
Settling within 1 LSB The INL is measured for 0+100mV to VDACR-100 mV The DNL is measured for 0+100 mV to VDACR-100 mV The DNL is measured for 0+100mV to VDACR-100 mV with VDDA > 2.4V
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Peripheral operating requirements and behaviors 5. Calculated by a best fit curve from VSS+100 mV to VREF-100 mV
Figure 16. Typical INL error vs. digital code
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Peripheral operating requirements and behaviors
Figure 17. Offset at half scale vs. temperature
6.6.4 Op-amp electrical specifications
Table 30. Op-amp electrical specifications
Symbol VDD ISUPPLY ISUPPLY VOS VOS IOS IOS IBIAS Description Operating voltage Supply current (IOUT=0mA, CL=0), low-power mode Supply current (IOUT=0mA, CL=0), high-speed mode Input offset voltage Input offset voltage temperature coefficient Input offset current (0~50C) Input offset current (-40~105C) Input bias current (0~50C) Min. 1.71 -- -- -- -- -- -- -- Table continues on the next page... Typ. -- 70 500 3 10 300 TBD 300 Max. 3.6 TBD TBD TBD -- -- -- -- Unit V A A mV V/C pA pA pA
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Table 30. Op-amp electrical specifications (continued)
Symbol IBIAS VCML VCMH RIN CIN |XIN| CMRR PSRR SR SR GBW GBW AV CL(max) ROUT VOUT IOUT GM PM Tsettle Tsettle Vn Vn Description Input bias current (0~105C) Input common mode voltage low Input common mode voltage high Input resistance Input capacitance AC input impedance (fIN=100kHz) Input common mode rejection ratio Power supply rejection ratio Slew rate (VIN=100mV), low-power mode Slew rate (VIN=100mV), high-speed mode Unity gain bandwidth, low-power mode Unity gain bandwidth, high-speed mode DC open-loop voltage gain Load capacitance driving capability Output resistance Output voltage range Output load current Gain margin Phase margin Settling time (Buffer mode, low-power mode) (To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k) Settling time (Buffer mode, high-speed mode) (To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k) Voltage noise density (noise floor) 1kHz Voltage noise density (noise floor) 10kHz Min. -- 0 -- 500 -- -- 60 60 0.1 1 0.15 1 80 -- -- 0.1 -- -- 45 -- -- -- -- Typ. TBD -- -- -- -- 50 -- -- -- -- -- -- 90 -- -- -- 0.5 20 56 TBD TBD 350 90 Max. -- -- VDD -- TBD -- -- -- -- -- -- -- -- TBD TBD TBD -- -- -- -- -- TBD TBD Unit pA V V M pF M dB dB V/s V/s MHz MHz dB pF V mA dB deg s s nV/Hz nV/Hz
6.6.5 Transimpedance amplifier electrical specifications -- full range
Table 31. TRIAMP full range operating requirements
Symbol VDDA VIN CL ROUT Description Supply voltage Input voltage range Output load capacitance Output resistance Min. 1.71 -0.2 3.6 VDDA-1.4 100 1500 Max. V V pf Unit Notes
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Table 32. TRIAMP full range operating behaviors
Symbol ISUPPLY ISUPPLY VOS VOS IOS IBIAS RIN CIN |XIN| CMRR PSRR SR SR GBW GBW AV VOUT IOUT GM PM Vn Vn Description Supply current (IOUT=0mA, CL=0) -- Low-power mode -- Min. 60 280 3 10 200 300 -- 17 TBD -- -- -- -- -- -- -- -- 0.5 20 60 280 100 Typ. -- -- TBD TBD TBD TBD -- -- -- -- -- -- -- -- -- -- VDD-0.15 -- -- -- -- -- Max. A A mV V/C pA pA M pF M dB dB V/s V/s MHz MHz dB V mA dB deg nV/Hz nV/Hz Unit Notes
Supply current (IOUT=0mA, CL=0) -- High-speed -- mode Input offset voltage Input offset voltage temperature coefficient Input offset current Input bias current Input resistance Input capacitance AC input impedance (fIN=100kHz) Input common mode rejection ratio Power supply rejection ratio Slew rate (VIN=100mV) -- Low-power mode Slew rate (VIN=100mV) -- High speed mode Unity gain bandwidth -- Low-power mode 50pF Unity gain bandwidth -- High speed mode 50pF DC open-loop voltage gain Output voltage range Output load current Gain margin Phase margin Voltage noise density (noise floor) 1kHz Voltage noise density (noise floor) 10kHz -- -- -- -- 500 -- -- 60 60 0.1 1 0.15 1 80 0.15 -- -- 50 -- --
Figure 18. Typical Open Loop Gain vs. Frequency [TBD] Figure 19. Typical Phase vs. Frequency [TBD]
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6.6.6 Transimpedance amplifier electrical specifications -- limited range
Table 33. TRIAMP limited range operating requirements
Symbol VDDA VIN TA CL ROUT Description Supply voltage Input voltage range Temperature Output load capacitance Output resistance 2.4 0.1 0 Min. 3.3 VDDA-1.4 50 100 1500 Max. V V C pf Unit Notes
Table 34. TRIAMP limited range operating behaviors
Symbol VOS VOS IOS IBIAS |XIN| CMRR PSRR SR SR GBW GBW AV GM PM Description Input offset voltage Input offset voltage temperature coefficient Input offset current Input bias current AC input impedance (fIN=100kHz) Input common mode rejection ratio Power supply rejection ratio Slew rate (VIN=100mV) -- Low-power mode Slew rate (VIN=100mV) -- High speed mode Unity gain bandwidth -- Low-power mode 50pF Unity gain bandwidth -- High speed mode 50pF DC open-loop voltage gain Gain margin Phase margin -- -- -- -- 500 -- -- 0.1 1 0.15 1 80 30 60 Min. 3 4 300 300 -- 70 70 -- -- -- -- -- -- 69 Typ. Max. TBD TBD TBD TBD -- -- -- -- -- -- -- -- -- -- mV V/C pA pA M dB dB V/s V/s MHz MHz dB dB deg Unit Notes
6.6.7 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol VDDA TA CL Description Supply voltage Temperature Output load capacitance Min. 1.71 -40 -- Max. 3.6 105 100 Unit V C nF Notes
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Table 36. VREF full-range operating behaviors
Symbol Vout Vout Vout Vstep Vdrift Ac Ibg Itr Description Voltage reference output with factory trim at nominal VDDA and temperature=25C Voltage reference output with factory trim Voltage reference output user trim Voltage reference trim step Temperature drift (Vmax -Vmin across the full temperature range) Aging coefficient Bandgap only (MODE_LV = 00) current Tight-regulation buffer (MODE_LV =10) current Load regulation (MODE_LV = 10) current = 1.0mA Tstup DC Buffer startup time Line regulation (power supply rejection) Min. TBD TBD 1.198 -- -- -- -- -- -- -- -- -60 Typ. 1.2 -- -- 0.5 -- -- -- -- -- -- -- -- Max. TBD TBD 1.202 -- 20 TBD TBD 1.1 TBD 100 TBD TBD Unit V V V mV mV ppm/year A mA V s mV dB See Figure 20 Notes
Table 37. VREF limited-range operating requirements
Symbol TA Description Temperature Min. 0 Max. 50 Unit C Notes
Table 38. VREF limited-range operating behaviors
Symbol Vout Description Voltage reference output with factory trim Min. TBD Max. TBD Unit V Notes
TBD
Figure 20. Typical output vs.temperature
TBD
Figure 21. Typical output vs. VDD
6.7 Timers
See General switching specifications.
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Peripheral operating requirements and behaviors
6.8 Communication interfaces
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 39. USB DCD electrical specifications
Symbol VDP_SRC VLGC IDP_SRC IDM_SINK RDM_DWN VDAT_REF Description USB_DP source voltage (up to 250 A) Threshold voltage for logic high USB_DP source current USB_DM sink current D- pulldown resistance for data pin contact detect Data detect voltage Min. TBD 0.8 7 50 14.25 0.25 Typ. TBD -- 10 100 -- TBD Max. TBD 2.0 13 150 24.8 0.4 Unit V V A A k V
6.8.3 USB VREG electrical specifications
Table 40. USB VREG electrical specifications
Symbol VREGIN IDDon IDDstby IDDoff Description Input supply voltage Quiescent current -- Run mode, load current equal zero, input supply (VREGIN) > 3.6 V Quiescent current -- Standby mode, load current equal zero Quiescent current -- Shutdown mode * VREGIN = 5.0 V and temperature=25C * Across operating voltage and temperature ILOADrun ILOADstby Maximum load current -- Run mode Maximum load current -- Standby mode -- -- -- -- 500 -- -- -- -- TBD 120 1 nA A mA mA Min. 2.7 -- -- Typ. -- 120 1 Max. 5.5 TBD TBD Unit V A A Notes
Table continues on the next page...
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Table 40. USB VREG electrical specifications (continued)
Symbol VReg33out Description Regulator output voltage -- Input supply (VREGIN) > 3.6 V * Run mode * Standby mode VReg33out COUT ESR ILIM Regulator output voltage -- Input supply (VREGIN) < 3.6 V, pass-through mode External output capacitor External output capacitor equivalent series resistance Current limitation threshold 3 2.5 2.3 1.76 1 185 3.3 2.8 -- 2.2 -- 290 3.6 3.6 3.6 8.16 100 395 V V V F m mA 1 Min. Typ. Max. Unit Notes
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
Table 41. Master mode DSPI timing (low-speed mode)
Num Operating voltage Frequency of operation DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DSPI_SCK output cycle time DSPI_SCK output high/low time DSPI_PCSn to DSPI_SCK output valid DSPI_SCK to DSPI_PCSn output hold DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold Description Min. 1.71 -- 4 x tBCLK (tSCK/2) - 4 (tSCK/2) - 4 (tSCK/2) - 4 -- -2 15 0 Max. 3.6 12.5 -- (tSCK/2) + 4 -- -- 10 -- -- -- Unit V MHz ns ns ns ns ns ns ns ns Notes 1
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced.
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DSPI_PCSn
DS3 DS2 DS1 DS4
DSPI_SCK (CPOL=0) DSPI_SIN
DS7 DS8
First data DS5
Data DS6 Data
Last data
DSPI_SOUT
First data
Last data
Figure 22. DSPI classic SPI timing -- master mode Table 42. Slave mode DSPI timing (low-speed mode)
Num Operating voltage Frequency of operation DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DSPI_SCK input cycle time DSPI_SCK input high/low time DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSIP_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven Description Min. 1.71 -- 8 x tBCLK (tSCK/2) - 4 -- 0 5 15 -- -- Max. 3.6 6.25 -- (tSCK/2) + 4 20 -- -- -- 15 15 Unit V MHz ns ns ns ns ns ns ns ns
DSPI_SS
DS10 DS9
DSPI_SCK (CPOL=0) DSPI_SOUT
DS13 DS15 DS12 First data DS14 First data Data Last data DS11 Data Last data DS16
DSPI_SIN
Figure 23. DSPI classic SPI timing -- slave mode
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6.8.5 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
Table 43. Master mode DSPI timing (high-speed mode)
Num Operating voltage Frequency of operation DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DSPI_SCK output cycle time DSPI_SCK output high/low time DSPI_PCSn to DSPI_SCK output valid DSPI_SCK to DSPI_PCSn output hold DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold Description Min. 2.7 -- 2 x tBCLK (tSCK/2) - 2 (tSCK/2) - 2 (tSCK/2) - 2 -- -2 TBD 0 Max. 3.6 25 -- (tSCK/2) + 2 -- -- 8.5 -- -- -- Unit V MHz ns ns ns ns ns ns ns ns
DSPI_PCSn
DS3 DS2 DS1 DS4
DSPI_SCK (CPOL=0) DSPI_SIN
DS7 DS8
First data DS5
Data DS6 Data
Last data
DSPI_SOUT
First data
Last data
Figure 24. DSPI classic SPI timing -- master mode Table 44. Slave mode DSPI timing (high-speed mode)
Num Operating voltage Frequency of operation DS9 DS10 DSPI_SCK input cycle time DSPI_SCK input high/low time Table continues on the next page... 4 x tBCLK (tSCK/2) - 2 Description Min. 2.7 Max. 3.6 12.5 -- (tSCK/2 + 2 Unit V MHz ns ns
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
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Peripheral operating requirements and behaviors
Table 44. Slave mode DSPI timing (high-speed mode) (continued)
Num DS11 DS12 DS13 DS14 DS15 DS16 Description DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSIP_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven Min. -- 0 2 7 -- -- Max. TBD -- -- -- 14 14 Unit ns ns ns ns ns ns
DSPI_SS
DS10 DS9
DSPI_SCK (CPOL=0) DSPI_SOUT
DS13 DS15 DS12 First data DS14 First data Data Last data DS11 Data Last data DS16
DSPI_SIN
Figure 25. DSPI classic SPI timing -- slave mode
6.8.6 I2C switching specifications
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
6.8.8 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Peripheral operating requirements and behaviors
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below.
Table 45. I2S master mode timing
Num Description Operating voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 I2S_MCLK cycle time I2S_MCLK pulse width high/low I2S_BCLK cycle time I2S_BCLK pulse width high/low I2S_BCLK to I2S_FS output valid I2S_BCLK to I2S_FS output invalid I2S_BCLK to I2S_TXD valid I2S_BCLK to I2S_TXD invalid I2S_RXD/I2S_FS input setup before I2S_BCLK I2S_RXD/I2S_FS input hold after I2S_BCLK Min. 2.7 2 x tSYS 45% 5 x tSYS 45% -- -2.5 -- -3 20 0 55% -- 55% 15 -- 15 -- -- -- Max. 3.6 Unit V ns MCLK period ns BCLK period ns ns ns ns ns ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4 S5
S4 S6
I2S_FS (output)
S9 S10
I2S_FS (input)
S7 S8
S7 S8
I2S_TXD
S9 S10
I2S_RXD
Figure 26. I2S timing -- master mode Table 46. I2S slave mode timing
Num Description Operating voltage S11 I2S_BCLK cycle time (input) Table continues on the next page... Min. 2.7 8 x tSYS Max. 3.6 -- Unit V ns
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Peripheral operating requirements and behaviors
Table 46. I2S slave mode timing (continued)
Num S12 S13 S14 S15 S16 S17 S18 Description I2S_BCLK pulse width high/low (input) I2S_FS input setup before I2S_BCLK I2S_FS input hold after I2S_BCLK I2S_BCLK to I2S_TXD/I2S_FS output valid I2S_BCLK to I2S_TXD/I2S_FS output invalid I2S_RXD setup before I2S_BCLK I2S_RXD hold after I2S_BCLK Min. 45% 10 3 -- 0 10 2 Max. 55% -- -- 20 -- -- -- Unit MCLK period ns ns ns ns ns ns
S11 S12
I2S_BCLK (input)
S15
S12 S16
I2S_FS (output)
S13 S14
I2S_FS (input)
S15 S16
S15 S16
I2S_TXD
S17 S18
I2S_RXD
Figure 27. I2S timing -- slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 47. TSI electrical specifications
Symbol VDDTSI CELE fREFmax fELEmax CREF VDELTA Description Operating voltage Target electrode capacitance range Reference oscillator frequency Electrode oscillator frequency Internal reference capacitor Oscillator delta voltage Min. 1.71 1 -- -- TBD TBD Typ. -- 20 5.5 0.5 1 600 Max. 3.6 500 TBD TBD TBD TBD Unit V pF MHz MHz pF mV 1 Notes
Table continues on the next page...
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
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Peripheral operating requirements and behaviors
Table 47. TSI electrical specifications (continued)
Symbol IREF IELE Pres5 Pres20 Pres100 Description Reference oscillator current source base current Electrode oscillator current source base current Electrode capacitance measurement precision Electrode capacitance measurement precision Electrode capacitance measurement precision Min. TBD TBD -- -- -- 0.003 0.003 -- 8 -- -- Typ. 1 1 TBD TBD TBD 0.25 -- -- 15 TBD 1 Max. TBD TBD TBD TBD TBD -- -- 16 25 -- TBD Unit A A % % % fF/count fF/count bits s A A 8 Notes 2 2 3 4 5 6 7
MaxSens2 Maximum sensitivity @ 20 pF electrode 0 MaxSens Res TCon20 ITSI_RUN ITSI_LP 1. 2. 3. 4. 5. 6. Maximum sensitivity Resolution Response time @ 20 pF Current added in run mode Low power mode current adder
The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 A, REFCHRG = 4), PS = 128, NSCN = 2; Iext = 16 (EXTCHRG = 15). 7. Typical value depends on the configuration used. 8. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, DELVOL = 2, EXTCHRG = 15.
6.9.2 LCD electrical characteristics
Table 48. LCD electricals
Symbol fFrame CLCD CBYLCD CGlass VIREG Description LCD frame frequency LCD charge pump capacitance -- nominal value LCD bypass capacitance -- nominal value LCD glass capacitance VIREG -- HREFSEL = 0 * HREFSEL = 0 * HREFSEL = 1 RTRIM VIREG TRIM resolution 0.89 1.49 3.0 Table continues on the next page... 1.00 1.67 -- 1.15 1.85 -- V V % VIREG Min. 28 -- -- -- Typ. 30 100 100 2000 Max. 58 -- -- 8000 Unit Hz nF nF pF 2 1 1 Notes
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
61
Dimensions
Table 48. LCD electricals (continued)
Symbol -- Description VIREG ripple * HREFSEL = 0 * HREFSEL = 1 IVIREG IRBIAS VIREG current adder -- RVEN = 1 RBIAS current adder * HREFSEL = 0 * HREFSEL = 1 RRBIAS RBIAS resistor values * LADJ = 00 or 01 -- Low load (LCD glass capacitance 2000 pF) * LADJ = 10 or 11 -- High load (LCD glass capacitance 8000 pF) VLL2 VLL2 voltage * HREFSEL = 0 * HREFSEL = 1 VLL3 VLL3 voltage * HREFSEL = 0 * HREFSEL = 1 3.0 - 5% 5 - 5% 3.0 5 -- -- V V 2.0 - 5% 3.3 - 5% 2.0 3.3 -- -- V V -- -- 0.28 2.98 -- -- M M -- -- 10 1 -- -- A A -- -- -- -- -- 1 30 50 -- mV mV A 3 3 Min. Typ. Max. Unit Notes
1. The actual value used could vary with tolerance. 2. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 3. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing's document number:
If you want the drawing for this package 80-pin LQFP 81-pin MAPBGA Then use this document number 98ASS23174W 98ASA10631D
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
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Pinout
8 Pinout
8.1 K51 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 81-pin ballmap assignments are currently being developed. The * in the entries in this package column indicate which signals are present on the package.
81 80 MAP LQF BGA P * * * * * * * * * 1 2 3 4 5 6 7 8 9 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
VDD VSS USB0_DP USB0_DM VOUT33 VREGIN
VDD VSS USB0_DP USB0_DM VOUT33 VREGIN
VDD VSS USB0_DP USB0_DM VOUT33 VREGIN
ADC0_DP1/ ADC0_DP1/ ADC0_DP1/ OP0_DP0 OP0_DP0 OP0_DP0 ADC0_DM1/ ADC0_DM1/ ADC0_DM1/ OP0_DM0 OP0_DM0 OP0_DM0 ADC1_DP1/ ADC1_DP1/ ADC1_DP1/ OP1_DP0/ OP1_DP0/ OP1_DP0/ OP1_DM1 OP1_DM1 OP1_DM1 ADC1_DM1/ ADC1_DM1/ ADC1_DM1/ OP1_DM0 OP1_DM0 OP1_DM0 PGA0_DP/ PGA0_DP/ PGA0_DP/ ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 PGA0_DM/ PGA0_DM/ PGA0_DM/ ADC0_DM0/ ADC0_DM0/ ADC0_DM0/ ADC1_DM3 ADC1_DM3 ADC1_DM3 PGA1_DP/ PGA1_DP/ PGA1_DP/ ADC1_DP0/ ADC1_DP0/ ADC1_DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 PGA1_DM/ PGA1_DM/ PGA1_DM/ ADC1_DM0/ ADC1_DM0/ ADC1_DM0/ ADC0_DM3 ADC0_DM3 ADC0_DM3 VDDA VREFH VDDA VREFH VDDA VREFH
* *
10 11
*
12
*
13
*
14
* *
15 16
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Pinout 81 80 MAP LQF BGA P * * * 17 18 19 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
VREFL VSSA ADC1_SE1 6/ OP1_OUT/ ADC0_SE2 2/OP0_DP2/ OP1_DP2 ADC0_SE1 6/ OP0_OUT/ CMP1_IN2/ ADC0_SE2 1/OP0_DP1/ OP1_DP1
VREFL VSSA ADC1_SE1 6/ OP1_OUT/ ADC0_SE2 2/OP0_DP2/ OP1_DP2 ADC0_SE1 6/ OP0_OUT/ CMP1_IN2/ ADC0_SE2 1/OP0_DP1/ OP1_DP1
VREFL VSSA ADC1_SE1 6/ OP1_OUT/ ADC0_SE2 2/OP0_DP2/ OP1_DP2 ADC0_SE1 6/ OP0_OUT/ CMP1_IN2/ ADC0_SE2 1/OP0_DP1/ OP1_DP1
*
20
*
21
VREF_OUT/ VREF_OUT VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE1 ADC1_SE1 8 8 TRI0_OUT/ OP1_DM2 TRI0_DM TRI0_DP TRI1_DM TRI1_DP TRI1_OUT/ ADC1_SE2 2 TRI0_OUT/ OP1_DM2 TRI0_DM TRI0_DP TRI1_DM TRI1_DP TRI1_OUT TRI0_OUT/ OP1_DM2 TRI0_DM TRI0_DP TRI1_DM TRI1_DP TRI1_OUT/ ADC1_SE2 2
* * * * * *
22 23 24 25 26 27
*
28
DAC0_OUT/ DAC0_OUT DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ ADC0_SE2 ADC0_SE2 3/OP0_DP4/ 3/OP0_DP4/ OP1_DP4 OP1_DP4 DAC1_OUT/ DAC1_OUT DAC1_OUT/ ADC1_SE2 ADC1_SE2 3/OP0_DP5/ 3/OP0_DP5/ OP1_DP5 OP1_DP5 XTAL32 EXTAL32 VBAT PTA0 XTAL32 EXTAL32 VBAT JTAG_TCL K/ SWD_CLK/ EZP_CLK JTAG_TDI/ EZP_DI XTAL32 EXTAL32 VBAT TSI0_CH1 PTA0 UART0_CT S_b FTM0_CH5 JTAG_TCL K/ SWD_CLK JTAG_TDI EZP_CLK
*
29
* * * *
30 31 32 33
*
34
PTA1
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
EZP_DI
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Pinout 81 80 MAP LQF BGA P * 35 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
PTA2
JTAG_TDO/ TSI0_CH3 TRACE_SW O/EZP_DO JTAG_TMS/ TSI0_CH4 SWD_DIO NMI_b/ EZP_CS_b VDD VSS EXTAL XTAL RESET_b LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 TSI0_CH5 VDD VSS EXTAL XTAL RESET_b
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO TRACE_SW O JTAG_TMS/ SWD_DIO NMI_b EZP_CS_b
* * * * * * * *
36 37 38 39 40 41 42 43
PTA3 PTA4 VDD VSS PTA18 PTA19 RESET_b PTB0
PTA3 PTA4
UART0_RT S_b
FTM0_CH0 FTM0_CH1
PTA18 PTA19
FTM0_FLT2 FTM_CLKIN 0 FTM1_FLT0 FTM_CLKIN 1 I2C0_SCL FTM1_CH0 LPT0_ALT1
LCD_P0/ PTB0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 LCD_P1/ PTB1 ADC0_SE9/ ADC1_SE9/ TSI0_CH6
FTM1_QD_ PHA
LCD_P0
*
44
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_ PHB
LCD_P1
*
45
PTB2
LCD_P2/ LCD_P2/ PTB2 ADC0_SE1 ADC0_SE1 2/TSI0_CH7 2/TSI0_CH7 LCD_P3/ LCD_P3/ PTB3 ADC0_SE1 ADC0_SE1 3/TSI0_CH8 3/TSI0_CH8 LCD_P8 LCD_P9 LCD_P10/ ADC1_SE1 4 LCD_P11/ ADC1_SE1 5 LCD_P12/ TSI0_CH9 LCD_P13/ TSI0_CH10 LCD_P14/ TSI0_CH11 LCD_P15/ TSI0_CH12 LCD_P20/ ADC0_SE1 LCD_P8 LCD_P9 LCD_P10/ ADC1_SE1 4 LCD_P11/ ADC1_SE1 5 LCD_P12/ TSI0_CH9 LCD_P13/ TSI0_CH10 LCD_P14/ TSI0_CH11 LCD_P15/ TSI0_CH12 LCD_P20/ ADC0_SE1 PTB8 PTB9 PTB10
I2C0_SCL
UART0_RT S_b UART0_CT S_b UART3_RT S_b
FTM0_FLT3 LCD_P2
*
46
PTB3
I2C0_SDA
FTM0_FLT0 LCD_P3
* * *
47 48 49
PTB8 PTB9 PTB10
LCD_P8 LCD_P9 FTM0_FLT1 LCD_P10
SPI1_PCS1 UART3_CT S_b SPI1_PCS0 UART3_RX
*
50
PTB11
PTB11
SPI1_SCK
UART3_TX
FTM0_FLT2 LCD_P11
* * * * *
51 52 53 54 55
PTB16 PTB17 PTB18 PTB19 PTC0
PTB16 PTB17 PTB18 PTB19 PTC0
SPI1_SOUT UART0_RX SPI1_SIN UART0_TX FTM2_CH0 FTM2_CH1 SPI0_PCS4 PDB0_EXT RG I2S0_TX_B CLK I2S0_TX_F S I2S0_TXD
EWM_IN EWM_OUT _b FTM2_QD_ PHA FTM2_QD_ PHB
LCD_P12 LCD_P13 LCD_P14 LCD_P15 LCD_P20
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
65
Pinout 81 80 MAP LQF BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
4/ TSI0_CH13 * 56 PTC1 LCD_P21/ ADC0_SE1 5/ TSI0_CH14 LCD_P22/ ADC0_SE4 b/ CMP1_IN0/ TSI0_CH15 LCD_P23/ CMP1_IN1 VSS VLL3 VLL2 VLL1 VCAP2 VCAP1 LCD_P24 LCD_P25 LCD_P26/ CMP0_IN0 LCD_P27/ CMP0_IN1 LCD_P28/ ADC1_SE4 b/ CMP0_IN2 LCD_P29/ ADC1_SE5 b/ CMP0_IN3 LCD_P30/ ADC1_SE6 b/ CMP0_IN4 LCD_P31/ ADC1_SE7 b LCD_P40 LCD_P41/ ADC0_SE5 b LCD_P42 LCD_P43
4/ TSI0_CH13 LCD_P21/ ADC0_SE1 5/ TSI0_CH14 LCD_P22/ ADC0_SE4 b/ CMP1_IN0/ TSI0_CH15 LCD_P23/ CMP1_IN1 VSS VLL3 VLL2 VLL1 VCAP2 VCAP1 LCD_P24 LCD_P25 LCD_P26/ CMP0_IN0 LCD_P27/ CMP0_IN1 LCD_P28/ ADC1_SE4 b/ CMP0_IN2 LCD_P29/ ADC1_SE5 b/ CMP0_IN3 LCD_P30/ ADC1_SE6 b/ CMP0_IN4 LCD_P31/ ADC1_SE7 b LCD_P40 LCD_P41/ ADC0_SE5 b LCD_P42 LCD_P43 PTC4 PTC5 PTC6 PTC7 PTC8 SPI0_PCS0 UART1_TX SPI0_SCK SPI0_SOUT PDB0_EXT RG SPI0_SIN I2S0_MCLK I2S0_CLKIN FTM0_CH3 LPT0_ALT2 CMP1_OUT LCD_P24 CMP0_OUT LCD_P25 LCD_P26 LCD_P27 LCD_P28 PTC1 SPI0_PCS3 UART1_RT S_b FTM0_CH0 LCD_P21
*
57
PTC2
PTC2
SPI0_PCS2 UART1_CT S_b
FTM0_CH1
LCD_P22
* * * * * * * * * * * *
58 59 60 61 62 63 64 65 66 67 68 69
PTC3 VSS VLL3 VLL2 VLL1 VCAP2 VCAP1 PTC4 PTC5 PTC6 PTC7 PTC8
PTC3
SPI0_PCS1 UART1_RX
FTM0_CH2
LCD_P23
*
70
PTC9
PTC9
I2S0_RX_B CLK
FTM2_FLT0 LCD_P29
*
71
PTC10
PTC10
I2C1_SCL
I2S0_RX_F S
LCD_P30
*
72
PTC11
PTC11
I2C1_SDA
I2S0_RXD
LCD_P31
* *
73 74
PTD0 PTD1
PTD0 PTD1
SPI0_PCS0 UART2_RT S_b SPI0_SCK UART2_CT S_b
LCD_P40 LCD_P41
* *
75 76
PTD2 PTD3
PTD2 PTD3
SPI0_SOUT UART2_RX SPI0_SIN UART2_TX
LCD_P42 LCD_P43
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Pinout 81 80 MAP LQF BGA P * * 77 78 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
PTD4 PTD5
LCD_P44 LCD_P45/ ADC0_SE6 b LCD_P46/ ADC0_SE7 b VSS LCD_P47
LCD_P44 LCD_P45/ ADC0_SE6 b LCD_P46/ ADC0_SE7 b VSS LCD_P47
PTD4 PTD5
SPI0_PCS1 UART0_RT S_b SPI0_PCS2 UART0_CT S_b SPI0_PCS3 UART0_RX
FTM0_CH4 FTM0_CH5
EWM_IN EWM_OUT _b
LCD_P44 LCD_P45
*
79
PTD6
PTD6
FTM0_CH6
FTM0_FLT0 LCD_P46
* *
-- 80
VSS PTD7
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1 LCD_P47
8.2 K51 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. NOTE The 81 MAPBGA ballmap assignments are currently being developed.
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
67
Revision History
VCAP1 VCAP2 PTD6 PTD2 PTC11 PTC10 PTC8 PTD7 PTD5 PTD3 PTC7 PTD4 PTD1 PTD0 PTC9 PTC6 PTC5 PTC4 VLL1 62 VLL2 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 25 26 28 29 31 23 24 27 32 35 30 36 33 34 37 38 39 40
79
75
72
71
69
80
78
76
68
77
74
73
70
67
66
65
64
VDD VSS USB0_DP USB0_DM VOUT33 VREGIN ADC0_DP1/OP0_DP0 ADC0_DM1/OP0_DM0 ADC1_DP1/OP1_DP0/OP1_DM1 ADC1_DM1/OP1_DM0 PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1_DM/ADC1_DM0/ADC0_DM3 VDDA VREFH VREFL VSSA ADC1_SE16/OP1_OUT/ ADC0_SE22/OP0_DP2/OP1_DP2 ADC0_SE16/OP0_OUT/CMP1_IN2/ ADC0_SE21/OP0_DP1/OP1_DP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
63
VLL3 VSS PTC3 PTC2 PTC1 PTC0 PTB19 PTB18 PTB17 PTB16 PTB11 PTB10 PTB9 PTB8 PTB3 PTB2 PTB1 PTB0 RESET_b PTA19
VREF_OUT/CMP1_IN5/ CMP0_IN5/ADC1_SE18
TRI0_OUT/OP1_DM2
TRI1_DM
DAC0_OUT/CMP1_IN3/ ADC0_SE23/OP0_DP4/OP1_DP4
DAC1_OUT/ADC1_SE23/ OP0_DP5/OP1_DP5
EXTAL32
TRI1_DP
TRI0_DM
TRI0_DP
TRI1_OUT/CMP2_IN5/ADC1_SE22
XTAL32
Figure 28. K51 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
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PTA18
VBAT
PTA2
PTA3
PTA1
PTA0
PTA4
VDD
VSS
Revision History
Table 49. Revision History
Rev. No. 2 3 4 Date 3/2011 3/2011 3/2011 Substantial Changes Initial public revision Added sections that were inadvertently removed in previous revision Reworded IIC footnote in "Voltage and Current Operating Requirements" table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
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Preliminary
69
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Document Number: K51P81M100SF2 Rev. 4, 3/2011
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